As of June 28th, 2022, the RISC-V spec1 reserves the PTE permission bit
combination of "write+!read", and the kernel would have incoherent behavior in
the last test case of "harness/cases/5.t". Since it leads to undefined behavior,
until further spec update, this test case should be disabled for RISC-V.
A patch to disallow such permission in mmap() can be found here2.
As of June 28th, 2022, the RISC-V spec1 reserves the PTE permission bit
combination of "write+!read", and the kernel would have incoherent behavior in
the last test case of "harness/cases/5.t". Since it leads to undefined behavior,
until further spec update, this test case should be disabled for RISC-V.
A patch to disallow such permission in mmap() can be found here2.